Today more than ever, we need high-speed circuits with low occupancy and low power as an alternative to CMOS circuits. Therefore, we proposed a new path to build nanoscale circuits such as Quantum-dot Cellular Automata (QCA). This technology is always prone to failure due to its very small size. Therefore, designers always try to design fault-tolerant gates and provide methods to increase the reliability of QCA. By adding redundant cells, the possibility of some defects such as cell omission and cell addition is somewhat reduced. However, in the face of defects such as stuck-at 0/1 faults, Clock fault and bridging fault. We can greatly increase the fault tolerance by appropriate placement and using fault tolerant gates with a suitable structure. In this paper, we design the XOR/XNOR gate with the approach of preventing stuck-at 0/1 fault, clock fault, and bridging fault using the first NNI gate tolerating cell addition fault.

Since, the characteristics of VLSI basic circuits like XOR/XNOR which are the result of single cell simulation setup, are not necessarily defining their behavior in multistage circuits, so reaching to different test methods and more suitable patterns are important issues for investigators in this field. In this paper a new method is proposed in which timing behavior of different circuits can be determined and compared so the result can be used in different structure configurations and large scale circuits. In addition to the new algorithm for designing XOR/XNOR balance circuits, two more new circuits have been proposed. By simulation tool, HSPICE, first sizing transistor due to PDP characteristics for circuits has been done and then their timing behaviors have been compared. The optimal circuit due to timing behavior is one of the novel methods. Simulations have been done by 0.18mm tmtechnology on the base of BS2M3v model.

Over the years, the design and implementation of fault-tolerant circuits have been one of the main concerns of the designers of electronic devices. Quantum Dot Cellular Automata (QCA) is a low-power, compact technology that is prone to various defects due to its small size. We can categorize these defects into three main groups: operational defects, manufacturing defects, and clocking defects. Using redundant cells, fault-tolerant gates, or changing the structure of the gates can improve the overall fault-tolerance of the circuit in some cases. However, increasing the fault-tolerance would lead to an increase in the occupied area and the delay of the gates. Therefore, designing a gate based on intercellular interactions with a minimum number of cells and maximum efficiency, which is also fault-tolerant, is a challenging task. In this paper, we present a new tile-shaped design for XOR and XNOR gates that is robust to the Missing cell, Extra cell, and Rotated cell defects by 25%, 55%, and 25%, respectively. That is why we call these gates TFXOR and TFXNOR, respectively.

Due to the main role of XOR-XNOR gates as the building blocks of many basic arithmetic circuits such as multiplexers, full adders, compressors etc, new methods of improving the speed and power consumption performance has been reported. As the dimensions have been reduced to deep submicron scale, noise immunity has also become an important parameter along with speed, power consumption and size. Herein, the functional properties of a number of these XORXNOR gates are compared and a new low power XOR-XNOR gates with improved noise immunity XOR-XNOR gates using 10 transistors is proposed. In passive defense issues, the immunity to electromagnetic disturbances is of paramount importance. Therefore increasing the circuits’ immunity to noise will help the circuits’ function properly against electromagnetic disturbances. The simulation results with 0.18 (mm) technology in an Hspice software for all supply ranges from 0.6 (V) to 3.3 (V) has shown that the new proposed circuit has lower power consumption, an improved PDP with better noise immunity compared to the previous reported circuits.

Background and Objectives: Recently, photonic crystals have been considered as the basic structures for the realization of various optical devices for high speed optical communication. Methods: In this research, two dimensional photonic crystals are used for designing all optical logic gates. A photonic crystal structure with a triangular lattice is proposed for making NAND, XNOR, and OR optical logic gates. Using the structure as the intended logic gate is possible without the need to change the structure through the use of the phase difference at the inputs. Line and point defects have been used to propagate light from inputs to output. The logical values "0" and "1", are defined based on the amount of transferred optical power to the output. Results: The simple structure and the use of line and point defects, instead of ring resonators, reduce the complexity of the design and its use in optical logic integrated circuits. Another advantage of proposed structure, in comparison to the previous structures is the reduction in delay time that increases its speed. The maximum delay time of the proposed optical NAND, XNOR, and OR gates is about 0. 1ps. Conclusion: In this study, one structure is suggested for realizing NAND, XNOR, and OR logic gates. This structure has a small size and low delay time, and is suitable for use in optical integrated circuits.

gate Induced Drain Leakage (GIDL) current is one of the main leakage current components in Silicon on Insulator (SOI) MOSFET structure and plays an important role in the data retention time of DRAM cells. GIDL can dominate the drain leakage current at zero bias and will limit the scalability of the structure for low power applications. In this paper we propose a novel technique for reducing GIDL and hence off-state current in the nanoscale single gate SOI MOSFET structure. The proposed structure employs asymmetric gate oxide thickness, which can reduce GIDL current, and hence Ioff current to about 98% in comparison with the symmetric gate oxide thickness structure, without sacrificing the driving current and losing gate control over the channel. This technique is very simple in the fabrication point of view in CMOS technology.